Japanese Patent Application No. 2001-143633 filed on May 14, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a transmission circuit, a data transfer control device, and electronic equipment.
In recent years, the Universal Serial Bus (USB) has attracted attention as an interface standard for connecting a personal computer with a peripheral device (electronic equipment in a broad sense). The USB has the advantage of enabling peripheral devices such as a mouse, keyboard, and printer, which are conventionally connected through connectors according to different standards, to be connected through the same standard connectors. Moreover, so-called plug and play and hot plug can be realized by the USB.
However, the USB has a problem in which the transfer rate is lower than that of the IEEE 1394, which has also attracted attention as a serial bus interface standard.
To deal with this problem, the USB 2.0 standard enabling a data transfer rate of 480 Mbps (HS mode), which is remarkably higher than that of the USB 1.1, while maintaining backward compatibility with the USB 1.1 standard has been developed and has attracted attention. The UTMI (USB 2.0 Transceiver Macrocell Interface) which defines the interface specification of the physical layer circuits and part of the logical layer circuits of the USB 2.0 has been also developed.
One aspect of the present invention relates to a transmission circuit which transmits a signal through first and second signal lines forming a differential pair, the transmission circuit comprising:
a current source connected between a first power supply and a given node;
a first switching device inserted between the node and the first signal line;
a second switching device inserted between the node and the second signal line; and
a third switching device inserted between the node and a second power supply,
wherein one of the first and second signal lines is driven by current from the current source through one of the first and second switching devices in a signal-transmission period, and
wherein the node is connected to the second power supply through the third switching device in a period other than the signal-transmission period.
Another aspect of the present invention relates to a transmission circuit which transmits a signal through a differential pair of first and second signal lines which are terminated at a given impedance Z0, the transmission circuit comprising:
a current source connected between a first power supply and a given node;
a first transistor which is inserted between the node and the first signal line and has an impedance substantially equal to an impedance Z0 when the first transistor is turned on;
a second transistor which is inserted between the node and the second signal line and has an impedance substantially equal to the impedance Z0 when the second transistor is turned on; and
a third transistor which is inserted between the node and a second power supply and has an impedance twice the impedance Z0 when the third transistor is turned on;
wherein one of the first and second signal lines is driven by the current source through one of the first and second transistors in a signal-transmission period, and
wherein the node is connected to the second power supply through the third transistor in a period other than the signal-transmission period.
Still another aspect of the present invention relates to a transmission circuit which transmits a signal through a differential pair of first and second signal lines which are terminated at a given impedance Z0, the transmission circuit comprising:
a current source connected between a first power supply and a given node;
first and second connection terminals connected to the first and second signal lines;
a third connection terminal connected to a second power supply outside the transmission circuit;
a first transistor which is inserted between the node and the first connection terminal and has an impedance substantially equal to an impedance Z0/2 when the first transistor is turned on;
a second transistor which is inserted between the node and the second connection terminal and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on;
a third transistor which is inserted between the node and the third connection terminal and has an impedance substantially equal to an impedance Z0 when the third transistor is turned on;
a first load element which is connected between a first transmission signal line connecting the first transistor with the first connection terminal and the second power supply, and has an impedance substantially equal to the impedance Z0; and
a second load element which is connected between a second transmission signal line connecting the second transistor with the second connection terminal and the second power supply, and has an impedance substantially equal to the impedance Z0,
wherein one of the first and second signal lines is driven by the current source through one of the first and second transistors in a signal-transmission period, and
wherein the node is connected to the second power supply through the third transistor in a period other than the signal-transmission period.